The invention relates to offset voltage circuits, and particularly relates to offset voltage circuits for use in digital data receiver systems.
A digital data receiver system typically includes some threshold detection circuitry for distinguishing between a high (or binary one) signal, and a low (or binary zero) signal. If the signals are relatively clean with respect to noise, then the threshold detection circuitry may simply set the threshold value to zero volts differential, and signals above zero volts differential are detected as a binary one, and signals below zero volts differential are detected as a binary zero.
Many digital data receiver systems, such as those that may be used with fiber optic communication systems, suffer from the presence of noise in the receiver signal. The presence of noise becomes potentially problematic if the noise causes the signal to cross the threshold, e.g., zero volts differential, within a single bit of information. One approach to reducing the noise is to include a capacitor in the receiver system that would integrate the signal with respect to time. This approach, however, limits the data clock speed of the receiver circuit due to the time delay required by the capacitor.
In certain communication systems, the noise in the received signal has been found to disproportionately affect the high signal to a greater extent than it affects the low signal. For example in receiver systems that include either an optical preamplifier or an avalanche photo diode, the high signal has been found to generally have more noise than the low signal Another approach, therefore, is to lower the threshold voltage by an offset voltage (e.g., 100 mv differential) that is tailored to the needs of the particular receiver system. Such offset circuits, however, typically provide non-linear responses to changes in adjustment voltages due to the non-ideal and non-linear characteristics of transistors within the offset circuitry itself, making proper adjustment difficult to achieve. The use of such adjustable offset voltage circuits, therefore, may have remained limited due to difficulties in setting the offset to a desired voltage.
There is a need, therefore, for an improved digital data receiver system that efficiently and accurately distinguishes between high and low data signals at high clock speeds.
There is a further need for an improved offset voltage circuit that provides a linear response to adjustment voltage inputs.
An adjustable offset voltage circuit is disclosed for applying an offset voltage to a differential voltage in a digital data receiver system. The circuit includes a pair of emitter follower units, and a pair of current generating units. The first emitter follower unit provides a first offset voltage, and the second emitter follower unit provides a second offset voltage. The first current generating unit provides a biasing current to the first emitter follower unit, and the second current generating unit provides a biasing current to the second emitter follower unit. The circuit also includes a pair of differential signal input ports, each of which is coupled to one of the first and second emitter follower units, and an offset adjustment unit for permitting offset adjustment of a differential output signal with respect to a differential input signal at the input ports. In an embodiment, the offset adjustment unit includes a, degenerated differential pair of transistors.